Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
As data transfer speeds have increased, high-speed differential serial lines have replaced large parallel buses in many designs. A Serializer/Deserializer (SERDES) converts parallel data into differential serial data, and differential serial data into parallel data. The interfacing requirements between a parallel data bus and a chip on a printed circuit board are implemented by a Protocol Controller device. To increase serial transmission speed, these parallel buses must increase either in width or in data speed. In the transmission of data, transceivers send and receive packets of data on serial data lines. The protocol controller creates or “frames” these packets, which are then sent to the SERDES for to the data processing logic or memory.
To provide higher bandwidth channel bonding is often used. Channel bonding is essentially a low-level load balancing technique that is accomplished by tying several serial channels together to create one logical aggregate channel. Several channels may be fed on a transmit side by one parallel bus and reproduced on a receive side as an identical parallel bus. The channel bonding match logic finds channel bond (CB) characters across word boundaries and performs a realignment of the data. A further description of channel bonding is found in Chapter 2 of the RocketIO™ Transceiver User Guide, ugO35, Jun. 29, 2004, from Xilinx Inc. of San Jose, Calif., which is herein incorporated by reference. Moreover, clock correction is needed when the rate that receive data is either slower or faster than the rate of retrieved data from a read side of a receiver.
Channel bonding and clock correction arbitration prevents packet corruption caused by match characters with insufficient spacing and also allows the user to tailor the response to the application. Clock correction and channel bonding circuits require a finite amount of time to execute their tasks and therefore require that the match characters in the packet be placed at specific intervals. If the characters are too closely spaced the circuits either ignore the character or corrupt the packet.
When correcting for misalignment, match characters cause the issuing of channel bonding (CB) requests. Packet buffer threshold indications can cause clock correction (CC) requests. If channel bonding (CB) requests and clock correction (CC) requests occur simultaneously, current implementations of channel bonding and clock correction do not allow for any adjustment and therefore force the user to adapt the packet to the circuit implementation.
It can be seen then that there is a need for a method and apparatus for providing channel bonding and clock correction arbitration in.